The present invention generally relates to semiconductor devices, and more particularly to a dynamic random access memory that has a stacked fin capacitor for increased capacitance of the memory cell capacitors.
The dynamic random access memories (DRAMs) are characterized by the simple device structure in that the device typically includes only a single memory cell capacitor for storing information and a single transfer gate transistor connected to the memory cell capacitor. Thus, the device can be fabricated easily with a large integration density and is suitable for constructing a semiconductor memory device having a large storage capacity. Currently, the devices having a storage capacity of 256 Mbits or 1 Gbits are studied intensively.
In order to fabricate large-scale DRAMs having a large number of memory cells assembled therein various efforts have been made so far. Such efforts of course include the development of the submicron patterning processes that are applicable to the fabrication of the DRAMs having extremely minute memory cells. Particularly, the development of optical lithography applicable to the submicron patterning is essential for the mass production of the DRAMs.
Simultaneously, considerable efforts have been developed for securing sufficient capacitance for the memory cell capacitors while reducing the size of memory cells simultaneously. It should be noted that the reduction of the size of the memory cell capacitor generally invites a reduction in the capacitance of the memory cell. In the DRAMs, the capacitance of the memory cell capacitors is required to be larger than the parasitic capacitance of the bit lines.
One obvious solution to compensate for such a decrease of the capacitance would be to increase the height of the memory cell capacitor such that a sufficient surface area is secured by the increased side wall area of the memory cell capacitor. This approach, however, causes a problem in that there appears a large difference in the level between a memory cell region wherein the memory cells are formed and a peripheral region wherein various peripheral circuits are formed. When such a large difference or step is formed on the surface of the device, the exposure of patterns particularly those extending between the memory cell region and the peripheral region across the boundary between these regions becomes extremely difficult or impossible. It should be noted that one has to use an optical system having a very large numerical aperture for conducting the exposure with submicron resolution, while the use of such a large numerical aperture inevitably reduces the focal depth of the optical system. In fact, an optical system having a focal depth in the order of 0.1 .mu.m has been used for the submicron optical exposure. In such a submicron optical exposure, the surface irregularity caused by the tall memory cell capacitors is detrimental.
In order to reduce the height of the memory cell capacitor and simultaneously to secure sufficient capacitance, the inventor of the present invention has proposed previously a stacked fin capacitor structure for the memory cell capacitor of the dynamic random access memories. In the stacked fin capacitor structure, a number of thin electrode plates or electrode fins are stacked with each other with a mutual separation and in connection with each other, and a thin dielectric film is deposited on the surface of the electrode fins. Further, an opposing electrode is provided to bury the stacked fin electrode by filling the space or gap formed between the electrode fins. Thereby, one can increase the surface area of the memory cell capacitor significantly without increasing the height.
FIGS. 1(A)-1(F) show a conventional process for fabricating a dynamic random access memory that uses the stacked fin structure for the memory cell capacitor.
Referring to FIGS. 1(A), a p-type silicon substrate 1 is subjected to an oxidation process in a wet O.sub.2 environment to form a field oxide film 1a of silicon oxide such that the field oxide film 1a covers the substrate 1 except for a device region in which the active part of the device is to be formed. Further, a tin oxide film 2 of silicon oxide is formed on the surface of the substrate 1 in correspondence to the device region by a thermal oxidation process which is conducted in a dry O.sub.2 environment. On the substrate 1 thus covered by the field oxide 1a and the oxide film 2, there is provided a polysilicon layer which is patterned subsequently to form a polysilicon word line WL. As usual, the word line WL extends over the oxide film 2 and acts as a gate electrode 3. Thereby, the oxide film 2 located underneath the gate electrode 3 acts as a gate oxide film.
After the gate electrode 3 is formed, an ion implantation of an n-type dopant such as As conducted in accordance with the self-alignment process that uses the gate electrode 3 as a mask, and there are formed diffusion regions 4 and 5 in the substrate 1 at both sides of the gate electrode 3 respectively in correspondence to the drain and source of a MOS transistor. Thereby, the MOS transistor forms a transfer gate transistor. Next, a silicon oxide insulation layer 7 is deposited on the device thus formed by a CVD process such that the word line WL is buried under the insulation layer 7. Further, a contact hole 8 is formed in the insulation layer 7 in correspondence to the source region 4 such that the surface of the substrate 1 and hence the source region 4 is exposed in correspondence to the contact hole 8, and a polysilicon layer is deposited on the layer 7 such that the polysilicon layer establishes a contact with the exposed surface of the source region 4. By patterning the polysilicon layer thus formed, a polysilicon bit line is formed. Thereby the structure of FIG. 1(A) is obtained.
On the structure of FIG. 1(A), a silicon nitride etching stopper 10 is deposited for example by a CVD process, and a silicon oxide layer 11 and a polysilicon layer 12 are deposited successively also by a CVD process. Further, another silicon oxide layer 13 is deposited on the polysilicon layer 12 similarly, and a contact hole 14 is formed through the layers 10-13 as well as through the underlying layers 2 and 7 to expose the upper major surface of the drain region 5 as shown in FIG. 1(B).
Next, a polysilicon layer 15 is deposited by a CVD process to cover the upper major surface of the silicon oxide layer 13 as well as the side wall of the contact hole 14 and further the surface of the drain region 5 exposed by the contact hole 14. Further, an RIE process is applied to form a groove 6 that extends substantially vertically from the upper major surface of the polysilicon layer 15 to the upper major surface of the etching stopper 11 such that the groove 6 defines each memory cell capacitor. In other words, each memory cell capacitor is separated from adjacent memory cell capacitors by the groove 6. See the structure of FIG. 1(C).
Next, an wet etching process using a HF etchant is applied to the structure of FIG. 1(C) to dissolve the silicon oxide layers 11 and 13. Thereby, the etching acts selectively upon silicon oxide and a structure shown in FIG. 1(D) is obtained. There, it will be noted that there is formed a stacked fin electrode 16 including a plurality of electrode fins formed of the polysilicon layers 12 and 15 such that the electrode structure 16 establishes a contact with the exposed upper major surface of the drain region 5.
Further, a silicon nitride film 17 is deposited on the exposed surface of the electrode 16 including the surface of the electrode fins 12 and 15 by a CVD process, and the structure thus formed is subjected to a thermal oxidation process for eliminating any pin holes formed in the silicon nitride film 17. Further, a polysilicon layer 18 is deposited also by a CVD process as an opposing electrode such that the polysilicon layer 18 fills the gap between the electrode fins and buries the electrode 16 underneath. Thereby, a dynamic random access memory as shown in FIG. 1(F) is obtained. In the device having the structure shown in FIG. 1(F), it will be noted that the surface area of the memory cell capacitor is increased significantly without increasing the height thereof. Thus, the device has been used successfully for the dynamic random access memories having the storage capacitor of up to 64 Mbits.
On the other hand, when the device having the structure of FIG. 1(F) is used for the DRAMs having a larger storage capacity such as 256 Mbits or more, the decrease of the thickness of the electrode fin becomes essential for compensating for the decreased capacitance. When the thickness of each electrode fin can be reduced successfully, the number of the fins and hence the capacitance of the memory cell capacitor would be increased. Thus, intensive investigations have been made to form the electrode fin as thin as possible.
In the effort to reduce the thickness of the electrode fin, the inventor of the present invention has discovered that there are cases wherein the electrode fins forming the stacked memory cell capacitor are deformed or bent as shown in FIG. 2. When this occurs, the electrode fins are contacted with each other and the capacitance of the memory cell capacitor is decreased inevitably. It was found further that such a deformation occurs particularly in the step of FIG. 1(D) for removing the oxide layers 11 and 13 by the wet etching process and in the step of providing the dielectric film 17 on the surface of the electrode fins. It is believed that the removal of the silicon oxide layer underlying the electrode fin causes the disappearance of the mechanical support of the electrode fin, and the electrode fin is subjected to a large thermal stress acting on the surface of the fin. Such a thermal stress is caused as a result of the difference in the thermal expansion between the polysilicon layer 12 or 15 and the silicon oxide layer 11 or 13. When the thermal stress exceeds the yielding strength of the polysilicon layer, the fin starts to cause a ductile deformation. Further, the deposition of the dielectric film 17 and the heat treatment applied thereto contributes to the ductile deformation of the electrode fin. It should be noted that the yielding strength of materials generally decreases at elevated temperatures because of the movement of dislocations which is facilitated in such elevated temperatures.
Further, it was found that the deformation of the electrode fin tends to appear most conspicuously in the electrode fin at the top of the stacked fin capacitor because of the cumulative effect of the thermal stress. It should be noted that there occurs an accumulation of the stress during each deposition of the polysilicon layers and the silicon oxide layers.